For ISDN or other applications, a communication switching system is required to switch data carried in standard time slots, each corresponding to a channel, grouped in frames. This has been typically done in ISDN systems by concatenating standard 64 kb/s channels.
Unfortunately, in many prior art switching systems, different channels in the same bit stream experienced different delays during the switching operation. This resulted in data getting out of order and becoming corrupted. Such a system is unacceptable for ISDN applications.
Data enters a switch in specific channels, and is stored. It is then switched by reading the store, and leaves the switch in different channels. Since the different output channels are not in the same sequence as the incoming channels, different delays result from the assignment of time slots to the data from that of the incoming bit stream.
One of the ways of eliminating the out of order problem due to differing delays on different channels has been to provide a constant delay to the data. In the past, this involved buffering an entire frame of data and then switching this buffered data one frame later. This provided the constant delay by giving maximum delay to all channels.
Constant delay was a requirement for data packet switches. In such systems, the packets of data were extracted from the data stream and were then switched individually through a switching mechanism.
Many inputs share a common physical interface. A protocol is established so that each of the input and output devices can share the bandwidth of the bus, but each has exclusive use of the bus during its period. Newer mechanisms allow many packets to be switched at once, but still extract the packets before switching.
The present invention assigns outgoing channels to incoming channels so that all channels are switched in order, but rather than with maximum delay as in the prior art, the present invention provides minimum delay. The present invention also allows the switching of constant bit rate channels of differing bit rates. It can provide channel assignment with a constant delay within one frame for concatenated communication channels, and allows the assignment of incoming and outgoing channels to provide an unambiguous constant delay period.
With proper alignment of delay between incoming and outgoing data streams, it is possible to provide constant delay switching. It is also possible to provide constant delay switching between streams of different data rates.
The term constant delay is intended to mean that the delay is a constant value of less than one frame. Constant delay is maintained here in contrast to packet based systems in which a packet is extracted and switched as a unit. Packet systems contain buffers to order packets and the ordering of packets in these buffers is not constant. Thus packet systems encounter variable delay due to the buffers which must be accounted for at the receiver by other buffers in the play out system. This variable delay is corrected by a delay buffer at play out. Thus variable packet delay is corrected by inserting a larger constant delay at the output. The present invention inserts a constant delay which needs no correction at the play-out point and so offers the minimum possible delay. Delay is an important impairment in multimedia systems and so reducing it and making it predictable are a great advantage offered by this technique.
In accordance with an embodiment of the invention, a method of assigning data from time slots on an input bus to time slots on an output bus is comprised of determining the order of time slots of data in a frame, determining whether each time slot of data in an input frame is to be located in the same or later time slot in an output frame, or whether it is to be located in an earlier time slot in an output frame; in the event each time slot of data of the input frame is to be located in the same or later time slot in an output frame, applying each time slot of data of the input frame to the same or a later time slot in the output frame; in the event a time slot of data of the input frame is to be located in an earlier time slot in an output frame, delay for one time slot interval and then apply each time slot of data of the input frame to the same or a later time slot in the output frame; whereby the order of time slots in a stream of output data is always from an earlier time slot to a later time slot.
In accordance with another embodiment, a method of assigning data from time slots on an input bus to time slots on an output bus is comprised of firstly connecting the time slots from the input bus to the time slots on the output bus in order beginning with the first of each time slot; in the event the first connecting step does not result in constant delay of time slots within a frame of data between the input and the output bus, secondly connecting the time slots from the input bus to the time slots on the output bus shifted one time slot later in time; and repeating the second connecting step until there is constant delay of time slots within a frame of data between the input and the output bus.